1. Field of the Invention
The embodiments of the invention relate to a semiconductor memory device, and more particularly, to a ferroelectric RAM (Random Access Memory) device provided with a cell array or word line driver suitable for high integration, and a method of driving the word line driver and the driving method to read and write data.
2. Description of the Related Art
Recently, ferroelectric thin films have been employed to a dielectric layer of a capacitor to improve a limitation of a refresh necessary for a DRAM (Dynamic Random Access Memory) device for the use a of large capacity of memory. A ferroelectric RAM (FeRAM) using such a ferro electric thin film has an advantage of preserving storage information under a cut-off state of power, as a kind of nonvolatile memory device, and advantages of high access, of reducing power consumption, and of strength against impact. Thus, the ferroelectric RAM is expected to be used as a main memory device in various kinds of electronic instruments and equipment having a file storage and a search function, such as a portable computer, a cellular phone, a game device, etc., or as recording media for recording sound or image.
In the ferroelectric DRAM device, ‘1’ or ‘0’ as data having a logical state is stored at a memory cell that is configured of a ferroelectric capacitor and an access transistor, in conformity with an electrically polarized state of the ferroelectric capacitor. When a voltage is applied to both terminals of the ferroelectric capacitor, ferroelectric material is polarized by a direction of an electric field, and a switching threshold voltage for which the polarization state of the ferroelectric material is changed, is called a coercive voltage. To read data stored in the memory cell, a voltage is applied between both electrodes of the ferroelectric capacitor so as to generate a potential difference, thus a state of data stored in the memory cell is sensed by a change of charge amount excited to a bit line.
FIG. 1 illustrates a general hysteresis curve of ferroelectric material. In the hysteresis curve, an X axis indicates a voltage applied to the ferroelectric material, namely, the voltage applied to both terminals of a capacitor under an assumption that among two electrodes of a ferroelectric capacitor, one electrode connected to a plate line is called a positive electrode and the other electrode is called a negative electrode. A Y axis indicates an amount of charge distributed to a surface thereof, in compliance with a spontaneous polarization of the ferroelectric material, that is, a polarization degree (μC/cm2).
Referring to FIG. 1, when a ground voltage Vss or 0V is applied, and thus there is no electric field applied to the ferroelectric material, a polarization is not generated. When voltage of both terminals in the ferroelectric capacitor increases to a positive direction, the polarization degree or charge amount increases from zero to a state point A of a positive polarization region. The polarization at the state point A is generated in one direction, and the polarization degree at the state point A reaches a maximum value. At this time, the polarization degree, due to the amount of charge kept in the ferroelectric material, is represented as Qs. After that, even though the voltage in both terminals of the capacitor again falls to the ground voltage Vss, the polarization degree does not fall to zero, but remains at a state point B. The residual polarization, due to the amount of charge contained in the ferroelectric material, namely, a residual polarization degree, is indicated as +Qr. Next, when the voltage of both terminals of the capacitor increases in a negative direction, the polarization degree is changed from the state point B to a state point C provided within a negative charge polarization region. At the state point C, the ferroelectric material is polarized in a direction opposite to the direction polarized at the state point A, and this polarization degree is represented as −Qs. Then, even though the voltage of both terminals of the capacitor again falls to the ground voltage Vss, the polarization degree does not fall to zero, but remains at a state point D. At this time, the residual polarization degree is indicated as −Qr. When the magnitude of voltage applied to both terminals of the capacitor again increases in a positive direction, the polarization degree of ferroelectric material is changed from the state point D to thestate point A.
As described above, when voltage for generating an electric field is applied one time to the ferroelectric capacitor in which ferroelectric material is inserted into two electrodes, a polarization direction is maintained in conformity with a spontaneous polarization even though the electrodes are determined as a floating state. A surface charge of the ferroelectric material through the spontaneous polarization is not naturally lost by a leakage etc. If the voltage is not applied in an opposite direction so that the polarization degree becomes zero, the polarization direction is maintained intact.
When the voltage is applied to the ferroelectric capacitor in a positive direction and is then removed, the residual polarization of ferroelectric material constituting the ferroelectric capacitor becomes a state of +Qr. When the voltage is applied to the ferroelectric capacitor in a negative direction and is then removed, the residual polarization of ferroelectric material becomes a state of −Qr. Herewith, it is assumed that in the residual polarization a logic state of +Qr state indicates data ‘0’, a logic state of −Qr state indicates data ‘1’.
FIG. 2 illustrates a memory cell constituting a memory cell array in a ferroelectric RAM device according to a prior art.
Referring to FIG. 2, the memory cell is constructed of one access transistor N1 and one ferroelectric capacitor C1. The access transistor N1 has two terminals, namely, a source terminal and a drain terminal, which are each connected between one electrode of the ferroelectric capacitor C1 and a bit line BL, and a gate thereof is connected to a word line. The other electrode of the ferroelectric capacitor C1's electrode, of which is connected to the access transistor N1, is connected to a plate line PL.
Read and write operations in the ferroelectric RAM device provided with the cell array are performed by an inversion of the above-described polarization, the cell array having a plurality of memory cells arranged in rows and columns. Thus, an operating speed of the ferroelectric RAM is decided by a polarization inversion time, and a polarization inversion speed is decided by an area of the capacitor, thickness of a ferroelectric thin film and an applied voltage etc.
FIGS. 3 and 4 are circuit diagrams of a cell array in a ferroelectric RAM according to the prior art. FIG. 3 is the circuit diagram of the ferroelectric RAM cell array based on an open or shared bit line structure. FIG. 4 is the circuit diagram of the ferroelectric RAM cell array based on a folded bit line structure.
As shown in FIGS. 3 and 4, the structure of the ferroelectric cell array is similar to the structure of a cell array of DRAM (Dynamic Random Access Memory), except in the use of a data storing capacitor in which ferroelectric material is used as a dielectric. That is, the ferroelectric RAM cell array is divided into opened and folded types in compliance with a bit line structure to sense data of a memory cell.
In the opened-type bit line structure of FIG. 3, memory cells 10 are arranged in a matrix, the memory cell 10 having a transistor N2 connected between a bit line BLi and a ferroelectric capacitor C2, wherein a gate of the capacitor N2 is connected to a word line WLi. The memory cells connected to the same bit line are each connected to mutually different plate lines PLi and PLi+1. Conversely, in the folded-type bit line structure of FIG. 4, array units 20 are arranged by a matrix so as to have more prominent degree of integration, and herewith, each one memory cell is connected with two adjacent bit lines BLi and BLi+1, and the memory cells are each connected to word lines WLi and WLi+1. Also, ferroelectric capacitors C3 forming the memory cells are connected commonly to one plate line.
An example for such an opened-type structure is disclosed in U.S. Pat. No. 6,137,711 patent granted to Agilent Technologies Inc. with the inventor of Charles M. C. Tan. One example of the folded-type structure is disclosed in U.S. Pat. No. 6,151,243 patent granted to Hyundai Electronics Inc. with the inventor of Jae Whan Kim.
FIG. 5 illustrates a word line driver circuit employed in the ferroelectric RAM device of the prior art.
As shown in FIG. 5, the word line driver circuit is constructed of four transistors and control signals. A word line decoding signal MWL is transferred to a gate of a transistor N5 through a transistor N4 operating by power source voltage VCC, to thus operate the transistor N5. The transistor N5 transfers an external power source voltage VPP having a level higher than the power source voltage to a word line. A discharge transistor N7 operating by a control signal WL_PDB is connected to the word line WL.
Before the word line driver operates, all control signals shown in FIG. 5 except a control signal WL_PDB have ground voltage Vss. When the operation starts, the word line decoding signal MWL is first applied as the power source VCC. Thus, a node voltage between the transistors N4 and N5 increases to a voltage VCC−Vth obtained by deducting a threshold voltage Vth of the transistor N4 from the power source voltage VCC. After a while, a control signal WL_DRV is applied as a level of the external power source voltage VPP, so that the node voltage is boosted to VCC−Vth+VPP by a capacitance between drain and gate of the transistor N5. Then, the transistor N5 has a sufficient gate voltage VCC−Vth+VPP and supplies sufficient current to the word line through the control signal WL_DRV. Therefore, a word line WL voltage reaches a level of the external power source voltage VPP. The access transistor of the memory cell connected to the word line WL is operated by a word line enable signal having the external power source voltage VPP.
Read and write operations in the ferroelectric RAM device of the prior art are described as follows, with reference to FIGS. 1 and 2.
To describe the read operation, it is assumed that data ‘1’ is stored in the ferroelectric capacitor C1 whose polarization state exists at the state point D. The state of the bit line BL is determined as the ground voltage Vss, and the word line enable signal is applied to the word line WL, to thus turn on the access transistor N1. When the power source voltage VCC is applied to the ferroelectric capacitor C1 through the plate line connected to a positive electrode of the ferroelectric capacitor C1, the polarization of the ferroelectric capacitor C1 is changed from the state point D to the state point A. A charge dQ1 corresponding to a state transition is transferred to the bit line BL through the access transistor N1. The charge transfer is detected through a sense amplification of a sense circuit connected to the bit line BL, such as a sense amplifier etc., and this designates that data value ‘1’ was read in the memory cell. A voltage of the bit line BL increases to the power source voltage VCC by the amplification operation of the sense amplifier, hence a polarization of the ferroelectric capacitor C1 is changed from the state point A to the state point B.
After reading the data ‘1’ from the memory cell, the same data ‘1’ on the bit line BL removes voltage applied to the plate line PL, thus producing a reverse state transition from the state point B to the state point C. Also, data ‘1’ is restored by changing the state point C to the state point D by determining the bit line BL voltage as the ground voltage Vss.
In the meantime, when data ‘0’ is stored in the ferroelectric capacitor C1 whose polarization state exists at the state point B, the word line enable signal is applied to the word line WL to turn on the access transistor N1, and the power source voltage VCC is applied to the plate line connected to the positive electrode of the ferroelectric capacitor C1. Then, the polarization of the ferroelectric capacitor C1 is changed from the state point B to the state point A. A charge dQ0 corresponding to such a state transition is transferred to the bit line BL through the access transistor N1. The charge transfer is detected through a sense amplification of a sense circuit connected to the bit line BL, such as a sense amplifier, etc., and this designates that data value ‘0’ was read from the memory cell.
A voltage of the bit line BL is determined as the ground voltage Vss by the amplification operation of the sense amplifier, and then a polarization of the ferroelectric capacitor C1 is changed from the state point A to the state point B, maintaining a logic state of data ‘0’, by removing the voltage of the plate line PL.
Next, in the write operation, to store data ‘1’ in the ferroelectric capacitor C1, the power source voltage VCC is applied to the ferroelectric capacitor C1 through the bit line BL and is then removed, then the polarization of the ferroelectric capacitor C1 is changed to the state point D through the state point C. The state that the polarization is formed at the state point D indicates a storage state of data ‘1’. Also, to store data ‘0’ in the ferroelectric capacitor C1, when the power source voltage VCC is applied to the ferroelectric capacitor C1 through the plate line PL and is then removed, the polarization of the ferroelectric capacitor C1 is changed to the state point B through the state point A. The state that the polarization is formed at the state point B indicates a storage state of data ‘0’.
General structure and operation of the ferroelectric RAM device according to the prior art is disclosed in U.S. Pat. No. 4,873,664 granted to Ramtron Corporation with the inventor of Eaton, Jr, et al., and in U.S. Pat. No. 5,978,251 granted to Ramtron International Corporation with the inventors of William F. Kraus et. al.
In the ferroelectric RAM device of the prior art, it may be desirable to connect more memory cells to one plate line in order to manufacture a ferroelectric RAM device of high integration. However, the ferroelectric capacitor has a large capacitance, thus a large charge pulse is necessary for an operation of the capacitor having a large capacitance. That is, a relatively large RC delay results from this large capacitance. This delay issue limits the number of memory cells connected to one plate line. The delay issue also requires more plate line drivers in the ferroelectric RAM of high integration. In other words, a memory chip size becomes large, power consumption increases and an operating time is prolonged. Furthermore, the word line driver of the prior art operates many transistors and several control signals, which is unsuitable for high integration, and there are shortcomings of high power consumption. In addition, the read and write operations are controlled by the plate line voltage and the bit line voltage, that is, data ‘1’ or ‘0’ can't be utilized in one time interval, thus an operating time is also lengthened.